I made this review on the Sandy Bridge chipset and today the time has come to put the mobile platform under microscope. We begin this article with a few words about what the new architecture for notebook market will see and will be the exact line-up of models for their processors. For the more curious of you I also recommend reading the previous articles on this technology because I will use some of the features there to draw conclusions at the end of this article. The names for the new processors are somewhat difficult to remember, as there are three series named differently, worthy of an engineer: Standard Voltage (SV), Low Voltage (LV) and ULV (Ultra Low Voltage).

The SV series are dealing with three dual – core models and three quad – cores and all have Hyper Threading activated. The three models with 4 – cores, the i7 – 2720 Q M, i7 – 2920 X M and the i7 – 2820 Q M ( mobile or desktop ) support native DDR 3 memory clocked at 1600 MHz. Probably this will help increase the performance of graphics performance due to extra bandwidth. What needs noting is that only quad – cores benefits from more than 4 MB of L3 cache, while the other models have to settle with only 3 MB, except the dual – core i7 – 2620 M that uses a 4 MB cache. All mobile processors have integrated graphics chipsets namely the Sandy Bridge Intel HD Graphics 3000 as opposed to models for the desktop market.

The models in the  LV / ULV Series core consists only of dual – cores, which benefit from 4 MB L3 caches, except for the i5 – 2537 M model with only 3 MB. Differences from the SV series are not very big, the main difference being smaller working frequencies for both the CPU and the integrated GPU if necessary to maintain power consuming. But we must keep in view that for a notebook that will run on these processors I am convinced that performance will be more than enough. One of the novelties that the Intel Sandy Bridge brings is to integrate graphics chip in the processor cores. The changes do not end there; we are talking about a massive optimization of communication between processors, the integration of cache LLC ( Last Level Cache ) L3 cache that works both as cache as well as graphics core, communicating with it through an bidirectional interface bus of “ring” type.